This invention is directed generally to improvements in the fabrication of semiconductor devices. It is particularly directed to the provision of improved isolation between a gate electrode and subsequent interconnect or gate levels and fabrication of adjacent, self-aligned transistors having independently formed gate dielectrics.
Conventional fabrication techniques frequently result in the inability to consistently provide adequate electrical isolation between a gate electrode and other subsequently formed gate electrodes or interconnects. Conventional attempts to improve such isolation have had limited success, principally because isolation oxides between various gate electrodes or interconnects are formed simultaneously with the formation of gate oxides. The simultaneous formation of the isolation and gate oxides prevents their being treated independently, even though they have independent requirements as to thickness and/or other characteristics. Typical of such conventional techniques is that described in the article entitled "Intermediate Oxide Formation in Double-Polysilicon Gate MOS Structure" in Volume 127, No. 11, of the Journal of the Electrochemical Society: Solid-State Science and Technology (November 1980).
Because of the foregoing problems, it has been difficult to consistently fabricate self-aligned transistor structures, such as where the gate dielectrics have different structures or are made of different materials.